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ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics
Characteristics noted under conditions 8.0V ≤ V PWR = V BAT ≤ 40V , -40 ° C ≤ T A ≤ 125 ° C, unless otherwise noted. Typical
values noted reflect the approximate parameter means at T A = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER INPUTS
VBAT Supply Voltage Startup Threshold (8)
V BAT_ST
–
6.0
8.0
V
VBAT Supply Current, V PWR = V BAT = 40V
RST and ENABLE = 5.0V
I BAT
mA
No output loads on Gate Drive Pins, No PWM
No output loads on Gate Drive Pins, 20kHz, 50% Duty Cycle
VPWR Supply Current, V PWR = V BAT = 40V
I PWR_ON
–
–
1.0
–
–
10
mA
RST and ENABLE = 5.0V
No output loads on Gate Drive Pins, No PWM
Output Loads = 620nC per FET, 20kHz PWM (9)
Sleep State Supply Current, RST = 0V
–
–
11
–
20
95
μA
V BAT = 40V
V PWR = 40V
I BAT
I PWR
–
–
14
56
30
100
Sleep State Output Gate Voltage
V GATESS
–
–
1.3
V
IG < 100μA
Trickle Charge Pump (Bootstrap Voltage)
V Boot
22
28
32
V
V BAT = 14V
Bootstrap Diode Forward Voltage at 10mA
V F
–
–
1.2
V
VDD V INTERNAL REGULATOR
V DD Output Voltage, V PWR = 8V to 40V, C = 0.47μF (10)
V DD
4.5
–
5.5
V
External Load I DD_EXT = 0 to 1.0mA
Internal V DD Supply Current, V DD = 5.5V, No External Load
I DD
–
–
12
mA
VLS REGULATOR
Peak Output Current, V PWR = 16V, V LS = 10V
I PEAK
350
600
800
mA
Linear Regulator Output Voltage, I VLS = 0 to
VLS Disable Threshold (12)
60mA (11)
V LS
V THVLS
13.5
7.5
15
8.0
17
8.5
V
V
Notes
8. When minimum system voltage could be less than 14V operation with the Charge Pump is recommended. V BAT must exceed this
threshold in order for the Charge Pump and V DD regulator to startup and drive V PWR to > 8.0V. Once V PWR exceeds 8.0V, the circuits
will continue to operate even if V BAT drops below 6.0V.
9.
10.
11.
12.
This parameter is guaranteed by design. It is not production tested.
Minimum external capacitor for stable V DD operation is 0.47μF.
Recommended external capacitor for the V LS regulator is 2.2μF low ESR at each pin VLS and VLS_CAP.
When V LS is less than this value, the outputs are disabled and HOLDOFF circuits are active.
33927
Analog Integrated Circuit Device Data
8
Freescale Semiconductor
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